The present invention relates to a clock recovery circuit for recovering a clock signal synchronized to the data that has been read out from a storage medium, like an optical or magnetic disk, by a digital data read channel.
To recognize an analog signal, read out from a storage medium, as digital data, a digital data read channel needs to recover a clock signal synchronized to the analog read signal. A clock recovery circuit is used for that purpose, i.e., to recover a clock signal from the analog read signal. The clock signal recovered will be used as sampling clock pulses for an analog-to-digital converter (ADC) or system clock pulses for a digital filter or Viterbi decoder.
A known clock recovery circuit recovers a clock signal by establishing single-loop feedback control. Specifically, the known clock recovery circuit receives, as an input signal, either the digital output of an ADC or a digital signal with a waveform shaped by a digital filter. By comparing that input signal to a reference clock signal, the circuit detects a phase difference between them and then controls the oscillation frequency of a voltage-controlled oscillator (VCO) in such a manner as to reduce the phase difference to zero. Then, the clock signal output from the VCO will be fed back as sampling clock pulses to the ADC.
However, if the known clock recovery circuit should cope with data to be transferred at a much higher rate, then the clock signal will be too much delayed by the ADC. The clock signal will also be delayed excessively where the digital filter should perform its filter operation as pipelined processing. That is to say, the clock signal is delayed by the feedback loop too much to acquire a sufficiently great loop gain. For that reason, a frequency lock range realized by the known clock recovery circuit is very narrow and it takes a long time for the known clock recovery circuit to accomplish phase locking completely.